1. Field of the Invention
The present invention generally relates to a method of making sub-lithographic elements, and, more particularly, to a method of achieving a minimum size image formed by the intersection of two spacers.
2. Description of the Related Art
One of the challenges to achieving higher levels of integration in semiconductor manufacturing is the patterning of smaller and smaller images. If the smallest images on a die are lithographically determined, the number of devices or circuits that can be placed in a given area is roughly inversely proportional to the square of the minimum lithographic dimension.
Since the fabrication cost of a region of silicon is not strongly related to the size of the minimum geometry in that region, it is prudent to package as many circuits in a given area as possible while maintaining a reasonable manufacturing yield to minimize circuit cost.
Some have developed procedures to produce sub-lithographic images, thereby allowing more dense integration with a concomitant reduction in per circuit costs. For example, U.S. Pat. No. 4,256,514, describes a method for forming sidewall spacers for fabricating sub-lithographic images consisting of narrow lines.
While useful for many applications, such sidewall image transfer (SIT) procedures typically produce an image that is sub-lithographic along one dimension only, usually the width of the image. Such one dimensional sub-lithographic procedures, however, are ineffective for applications that seek smaller contact regions, which require small, sub-lithographic geometries in two dimensions.
In light of the foregoing, there exists a need for a method to achieve images that have sub-lithographic dimensions along two axes.